In digital circuits the two logical states of a wire are usually represented by two different voltages. When a wire voltage is below a predetermined threshold, the signal on the wire is read as “low.” When a wire voltage is above a predetermined threshold, the signal on the wire is read as “high.” A logic high voltage is often referred to as Vdd, and a logic low voltage is often referred to as Vss, which is the digital “ground.” In modern digital logic systems, different Vdd levels are often utilized for different functional circuit blocks to manage system performance and power consumption. For example, certain circuit blocks do not need to operate as fast as other circuit blocks. Therefore, the Vdd for certain circuit blocks may be set at a different level than the Vdd for other circuit blocks. A functional circuit block's Vdd level is often referred to as the circuit block's power domain. When digital signals are transferred from a circuit block operating in one power domain to a circuit block operating in another power domain, the signals need to be converted from one power domain to another. Level shifter circuitry shifts signals from one power domain to another, and is often used as an interface between a functional circuit block operating in power domain A and a functional block operating in power domain B. Providing multiple power domains also requires multiple power rails, which increases power rail physical routing congestion on the integrated circuit.
Power consumption and area efficiency are critical problems in today's small, high-speed and high-performance mobile applications. In so-called system-on-chip (SoC) designs, a common technique to reduce power consumption is to divide the system into different power domains. For example, at a coarse level, computational logic and cache can be designed to operate at their own supply voltages. In systems that provide multiple processing cores on the same chip (i.e., multi-core systems), multiple power domains are required to facilitate dynamic voltage and frequency scaling (DVFS) for each core. Generally, providing finer granularity power domains is known to reduce system power effectively and is considered an attractive approach to addressing the power wall problem. As described above, multi-domain designs require some type of level shifter circuitry at the domain boundary to assure reliable cross domain data transfer and manage cross domain data traffic. However, known attempts to provide level shifter circuitry in small, high-speed and high-performance applications have been impractical because of inefficiencies in various performance parameters, such as area consumption, power consumption, write time delay, power rail congestion, and others. These challenges have hindered the widespread acceptance of fine-grained multi-power domain system designs.
Examples of known attempts to integrate a level shifter with a multi-stage flip-flop (e.g., a master-slave flip-flop) that operates across multiple power domains include Fujio Ishiha, Level conversion for Dual-Supply Systems, in Trans. VLSI System, 2004; and H. Mahmoodi-Meimand, A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme, in Proc. CICC, 1998. However, the induced area penalty and difficulties of providing multi-power supply voltages within local cell levels inhibits the broad acceptance in 2D IC designs. The deficiencies of these designs include (i) the presence of a feedback signal path from the high power stage through the pass gate to the low power stage, and (ii) a lack of write enhancement considerations on the level shifter stage, which increases delay, leakage and dynamic power. These deficiencies are even more severe in smaller feather size designs.
Accordingly, there is a need for integrated circuit level shifter designs and implementation techniques that address and improve various performance parameters including area consumption, power consumption, cross-talk across power domains, write time delay, power rail congestion, and others.